(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method of filling shallow trenches, in shallow trench isolation, STI sub-quarter micron technology. The present method relates to a method for forming of void-free trench gap fill with chemically vapor deposited (CVD) silicon oxide films using a layer of silicon dioxide liner deposited from a TEOS-ozone mixture at atmospheric pressure chemical vapor deposition (APCVD) or at sub-atmospheric pressure thermal chemical vapor deposition (SACVD) conditions, within trenches within substrates employed in integrated circuit fabrication.
(2) Description of Prior Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuits elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed silicon dioxide isolation (ROI) methods to form trench isolation regions nominally coplanar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. There are some process problems in the prior art associated with shallow trench isolation (STI) and the integration of trench filling by silicon dioxide films.
Process problems that arise under certain conditions are the formation of voids and seams in the isolating dielectrics employed in the trench fill process. One reason for the void and seam formation is shown as prior art, sketched in sequence in FIGS. 1a to 1d. A semiconductor substrate 2 is shown; a layer of pad thermal silicon dioxide 4 has been grown on the surface of the substrate 2 and a layer of pad silicon nitride 6 has been deposited over the layer of pad thermal silicon dioxide. A trench 8 has been etched through the silicon nitride 6 and pad silicon dioxide 4 films and partially into the substrate 2, followed by thermal silicon dioxide 10 growth inside the trench 8. An isolation dielectric such as silicon dioxide is deposited over the silicon wafer to fill the STI trench either using chemical vapor deposition (CVD) technique, such as low pressure TEOS (tetraethylorthosilicate) (LPCVD), or TEOS-ozone atmospheric pressure (APCVD), or sub-atmospheric pressure (SACVD), as shown in FIG. 1c (12), or high-density plasma CVD (HDP-CVD), as shown in FIG. 1d (15).
Problems arise as shown in FIG. 1b: a) imperfect regions A (sharp edges) after thermal oxidation where thermal silicon dioxide 10 meets the pad silicon dioxide 4 and silicon nitride pad 6, b) imperfect regions B (high sidewall angles) after thermal oxidation where thermal silicon dioxide 10 forms the side of the trench, c) imperfect regions C (sharp edges) after thermal oxidation where thermal silicon dioxide 10 meets the lower portion of the trench.
As can be seen in FIG. 1c and FIG. 1d, seams 16 and voids 14 have formed in the isolation silicon dioxide dielectric, which fills the trench. The likelihood of these voids and seams forming increases as the aspect ratio of the trench increases. The aspect ratio is the ratio between the depth of the trench and the width of the trench. It is observed in the art that voids will form in the isolation dielectrics if the aspect ratio is greater than about 1:1 for low pressure TEOS LPCVD silicon dioxide, and about 2:1 for TEOS-ozone APCVD or SACVD, as well as, for high-density plasma CVD silicon dioxide. Unfortunately, aspect ratios exceeding 2:1, and even approaching 4:1, and higher are needed, as integrated circuit device geometry continues to decrease. Moreover, the problem of trench filling increases with further increases in the slope of the trench sidewall, along with the decrease of trench size. Furthermore, if voids formation occurs, then the surface conductive layers, which are subsequently deposited can get trapped in the voids, leaving a conductive, deleterious residue behind. These trapped conductive residues can then cause electrical shorting paths between layer elements, that are designed to be electrically isolated.
Related patents follow, which teach various methods of shallow trench isolation (STI).
U.S. Pat. No. 5,740,740 entitled "Shallow Trench Isolation (STI) Method Employing Gap Filling Silicon Oxide Dielectric Layer" granted Apr. 21, 1998 to Jang et al describes a method for filling a trench within a silicon substrate. Several process steps are employed to fill the trench: a) a thermal silicon oxide trench liner layer, b) an intermediate layer formed through plasma enhanced chemical vapor deposition (PECVD), which is used to suppress surface sensitivity affects, employing silane silicon source material, c) a gap filling silicon dioxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) employing, tetra-ethyl-ortho-silicate (TEOS).
U.S. Pat. No. 5,801,083 entitled "Use of Polymer Spacers for the Fabrication of Shallow Trench Isolation Regions with Rounded Top Corners" granted Sep. 1, 1998 to Yu et al describes a method for filling shallow trench isolation (STI) regions, with rounded corners. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. The sharp corner, at the intersection between the shallow trench and the unreacted region of semiconductor, is converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner "wrap-around".
U.S. Pat. No. 5,447,884 entitled "Shallow Trench Isolation with Thin Nitride Liner" granted Sep. 5, 1995 to Fahey et al shows a method of forming shallow trench isolation (STI) with a silicon nitride liner layer of less than 5 nm in thickness. A densification step of a pyrogenic oxide anneal at 800 degrees Centigrade drives out impurities and densities the material.
U.S. Pat. No. 5,726,090 entitled "Gap-filling of O.sub.3 -TEOS for Shallow Trench Isolation" granted Mar. 10,1998 to Jang et al shows a method of gap filling shallow isolation with TEOS-ozone silicon dioxide. Trenches are formed and a thermal oxide layer is grown within the isolation trenches. A plasma enhanced silane-based silicon dioxide layer is deposited over thermal silicon dioxide layer within the isolation trenches and treated with nitrogen gas plasma. Thereafter, a TEOS-ozone tetra-ethyl-ortho-silicate silicon dioxide layer is deposited overlying the plasma enchanced silicon dioxide, which is used for both the suppression of the surface sensitivity affects and for filling the isolation trenches. The excess TEOS-ozone deposited layer and the plasma enhanced silicon dioxide layer are polished away.
U.S. Pat. No. 5,786,262 entitled "Self-Planarized Gap filling for Shallow Trench Isolation" granted Jul. 28, 1998 to Jang et al describes a method to form a shallow trench isolation (STI) with a TEOS-ozone tetra-ethyl-ortho-silicate silicon dioxide, as a gap filling material. After the trench is formed, a TEOS-ozone silicon dioxide layer is formed in the shallow trench. Next, chemical mechanical polish (CMP) is performed to make the surface of the substrate planar. This is then followed by a thermal anneal to densify the remaining TEOS-ozone silicon dioxide layer.